The storage of information on computer systems and in embedded chips for smartcards, etc. becomes more and more important. Particularly, flash memory arrays may be employed for this purpose.
SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) and charge trapping memories in general (for instance nanocrystals, SONOS with one or more layers made of a high k-material, etc.) are serious candidates for embedded and stand alone non-volatile memories in the 45 nm CMOS generation and beyond, thanks to the ease of integration in the CMOS flow and the low program and erase voltages compared to floating gate devices.
However, data retention of SONOS memory cells may be insufficiently small. In fact, SONOS cells are operated by direct tunneling in both programming and erasing. An advantage of direct tunneling is that it requires extremely low current values (in the order of magnitude of pico amperes) so that a large amount of cells (for instance more than 106 cells) may be programmed or erased at the same time, at the expense of relatively high voltages (for instance 10 V to 13 V). However, when implementing direct tunneling processes, the bottom silicon oxide thickness of a SONOS transistor cannot be increased above approximately 2.5 nanometer (nm) to improve the data retention time because the hole tunneling from the substrate to the silicon nitride during erasing may become extremely low and the erasing may become inefficient.
Such a scenario is shown in a diagram 200 illustrated in FIG. 2.
The diagram 200 comprises an abscissa 201 along which a time is plotted in seconds. Along an ordinate 202, a threshold voltage VT is plotted in Volt. A first curve 203 is assigned to a bottom oxide having a thickness of approximately 2.2 nm, whereas a second curve 204 is assigned to a bottom oxide having a thickness of approximately 2.4 nm. FIG. 2 illustrates erase curves 203, 204 obtained by tunneling in SONOS devices with 2.2 nm/6 nm/8 nm and 2.4 nm/6 nm/8 nm ONO (silicon oxide-silicon nitride-silicon oxide) stacks. The curves 203, 204 are very sensitive to bottom oxide thickness.
FIG. 3 illustrates a diagram 300 for a bottom oxide having a thickness of 3 nm and showing different curves correlated to different control gate voltages Vcg. FIG. 3 shows erase curves for a SONOS device with a 3 nm/6 nm/8 nm ONO stack for different gate voltages. As may be taken from FIG. 3, erase is simply not possible.
From FIG. 2 and FIG. 3, it may be taken that it may be very difficult to improve the retention time of a SONOS device operated by tunneling procedures.
US 2004/0155234 A1 discloses a non-volatile semiconductor memory device comprising an ONO film constituted by a silicon nitride film for accumulating charge and by oxide films disposed thereon and thereunder, a memory gate electrode disposed at an upper portion thereof, a select gate electrode disposed at a side portion thereof through the ONO film, a gate oxide film disposed thereunder. By applying a potential to a select gate electrode of a memory cell having a source region and a drain region and to the source region and by accelerating electrons flowing in a channel through a high electric field produced between a channel end of the select memory transistor and an end of an n-type doped region disposed under the memory gate electrode, hot holes are generated by impact ionization, and the hot holes are injected into a silicon nitride film by a negative potential applied to the memory gate electrode, and thereby an erase operation is performed.
However, the retention time of a memory arrangement according to US 2004/0155234 A1 may be insufficient.